In the past decade, the state-of-the-art silicon-based electronics has gone from devices at or above 100 nm to the realm of 30 nm and below. In order to address the power issues the industry is facing as CMOS devices are scaled further, a program called Nanoelectronic Research Initiative was created to develop new materials and devices that take advantage of new state variables with the objective of improving performance per power density. Graphene, a monolayer of carbon atoms arranged in a honeycomb lattice, has recently been subject of considerable theoretical and experimental interest because of its unique transport properties together with exceptional chemical and physical properties. New devices taking advantage of the theoretical prediction on the existence of a Bose-Einstein condensate in bi-layer graphene films, graphene based tunnel FETs, lateral tunnel FETs, and Veselago lens based devices have been proposed. However, in order to demonstrate that any of the proposed can meet the most basic device requirements, high quality films will have to be developed and integrated with dielectrics and metal contacts. We will review the need for devices beyond CMOS, growth of large area graphene and integration of dielectrics and metal contacts with graphene and their effects on field effect transistors characteristics.